According to speed-up of a CPU, a demand for improvement of an operation frequency of a semiconductor memory is increasing year after year. In a conventional synchronous dynamic random access memory (SDRAM), speed-up has been achieved by raising an integration degree based upon miniaturization. In a double data rate synchronous dynamic random access memory (DDR SDRAM) which is currently mainstream, a data transfer rate has been improved by utilizing a prefetch operation which previously reads a plurality of bits stored in a memory array and an interface system that outputs the plurality of data in a time-series manner in synchronism with both edges of a clock.
An amount of data read from a memory array at one time according to the prefetch operation of the DDR SDRAM relates to the data transfer rate, and it varies according to generation. For example, in a first generation (hereinafter, called “DDR”) of the DDR SDRAM, a data transfer rate of 200 megabits to 400 megabits per second has been realized according to a two-bit prefetch operation reading stored data of two bits at one time. In a second generation (hereinafter, called “DDR-II”), realization of a data transfer rate of 400 megabits to 800 megabits per second is intended according to a four-bit prefetch operation reading stored data of four bits at one time. In a third generation (hereinafter, called “DDR-III”), the data transfer rate may reach 800 megabits to 1600 megabits per second according to an eight-bit prefetch operation reading stored data of eight bits at one time. From such differences in prefetch number among generations, the prefetch system in the DDR SDRAM is specifically called “2N bit prefetch system (N is an integer)”.
When a DDR SDRAM with storage capacity of Gigabit class is realized according to advance of miniaturization in the future, since there is a possibility that a chip area exceeds 100 square millimeters and so, it becomes difficult to maintain operation rates of a memory array and an input/output bus (inside a chip) constant, which may result in increase in access time. For example, since device characteristic fluctuation of a MOS transistor constituting a memory cell transistor or a sense amplifier increases according to voltage lowering or miniaturization, an operation margin of a memory array may degrade. Since a memory array configuration using a multi-divided bit line and a multi-divided word line effective for expansion of an operation margin according to increase of a read signal amount directly provokes increase in the number of peripheral circuits such as a sense amplifier or a word driver. Therefore, since the number of divisions is limited, it is difficult to obtain a dramatic effect. In a path for transferring data read from the memory array to an output buffer, a wiring length of the path increases, which may result in lowering in internal operation rate of a chip due to increase of RC delay.
As to an operation rate of an input/output bus, an approach for reducing a time period required to transfer data read from the memory array to an input/output circuit is disclosed in Japanese Patent Laid-Open No. JP 2002-25265, for example. Specifically, focusing attention on a line from a main amplifier to an output buffer contained on the path, data to be first outputted from data of 2N bits prefetched is read using a high-speed main amplifier and a global input/output line (GIO) with low impedance. Subsequent data is read using an ordinary main amplifier. According to such a constitution and an operation, an access time is reduced while power consumption is being suppressed.